In high-performance high-speed links, lane deterministic jitter (DJ) due to clock duty-cycle distortion (DCD) may be a significant fraction of the total lane deterministic jitter. In low-power high-performance links, due to the small size of the I/O driver circuits, systems and methods of calibration may be important for meeting duty-cycle distortion specifications. A large portion of deterministic jitter in a serial data transmitter may be caused by duty-cycle distortion (DCD) of the double data rate clock, and the mismatch in the output multiplexer (OMUX).
Thus, there is a need for a system and method for reducing duty-cycle distortion in a serial data transmitter.